In recent years, a programmable logic, such as FPGA (Field Programmable Gate Array), constitutes a data processing circuit for specific application in many products. Previously, the FPGA has been often used as a tool for debugging in research and development. The use of the circuit that can be constituted by the FPGA has been expanded along with an improvement in the LSI manufacturing technology, and the manufacturing cost is reduced. Therefore, there is a trend of mounting the FPGA on various products. The cost can be particularly reduced in small-lot products compared to when ASIC (Application Specific Integrated Circuit) constitutes a data processing circuit for a specific application.
However, in general, the circuit operation and the processing speed of the FPGA may be inferior to those of the ASIC. On the other hand, the FPGA can reconfigure the wiring to connect the logic to reconfigure functions of the FPGA. Therefore, the wiring can be reconfigured in accordance with the functions of the data processing circuit adopting the FPGA. For example, if the image processing circuit of a multi function device (multi function peripheral) is constituted by the FPGA, the functions of the FPGA can be reconfigured in accordance with a scan job, a copy job, and a print job that are available by the multi function device. As a result, an optimal image processing circuit can be constituted in accordance with a job designated by the user, and the performance of the image processing circuit can be improved. Furthermore, there is no need to include processing circuits of hardware corresponding to each job, and the overall circuit size can be reduced. Japanese Patent No. 3834935 (D1) proposes reconfiguration of a configuration of a circuit using the FPGA to process drawing elements, such as characters, figures, and images, using a predetermined drawing command.
To reconfigure the functions of the FPGA, an additional controller is necessary to reconfigure wiring information of the FPGA. Therefore, for example, the following process needs to be executed in the multi function device using the FPGA. For example, when the user inputs a print job into the multi function device from a PC via a network, a main CPU of the multi function device that has received the print job determines whether or not reconfiguration of the functions of the image processing circuit is necessary. If the main CPU determines that the reconfiguration of the functions is necessary, the main CPU temporarily stores the print job received from the PC in a storage device such as an HDD and reconfigures the functions of the FPGA constituting the image processing circuit to process the print job. When the reconfiguration of the functions is completed, the main CPU supplies the print data stored in the storage device to the image processing circuit, and the image processing circuit executes image processing. Therefore, there is a problem that the print data cannot be supplied to the image processing circuit constituted by the FPGA during the reconfiguration of the functions of the FPGA.
Japanese Patent Laid-Open No. 2004-48228 (D2) discloses a technique, in which when an external circuit inputs an initialization signal before writing of a programmable logic unit is completed, active/inactive of the initialization signal is determined to respond to the external circuit. In the invention of D2, there is no need for the external circuit to determine whether the wiring of the programmable logic unit is being reconfigured.